This invention relates to a semiconductor device and its manufacture method, and especially to a MIS (Metal-Insulator-Semiconductor) type semiconductor device having a gate insulating film which comprising a material, such as a metal oxide that has a dielectric constant higher than silicon oxide, and to its manufacture method.
Miniaturization of MOS transistors is continuously advanced, and 0.1-micrometer gate length is almost being realized. This is because the “reduction rule/scaling rule” is still effective, where a miniaturization of semiconductor elements leads to a high speed operation and a lower power consumption the semiconductor devices. On the other hand, by making a semiconductor element smaller, occupancy area of the element is reduced and more elements can be integrated in the same chip area. As a result, LSI can be multi-functionalized. Also from this point, it is worthy of pursuing a miniaturization of a semiconductor element.
However, it is expected that pursuit of a reduction rule collides with a big wall bordering on 0.1 micrometers. That is, an approach to make a thinner gate oxidization film is coming to a limit.
Conventionally, SiO2 (silicon oxide) has been used as a material of an insulating film provided in the bottom of a gate electrode. This is because the insulating film hardly contains a fixed electric charge, and because undesirable energy levels at interface between silicon and the insulating film at a channel area are hardly formed. These two special features are indispensable in order to obtain a good operation of a semiconductor element. A silicon oxide also has a feature that a thin film can be easily formed with sufficient controllability of the thickness.
However, the relative dielectric constant of SiO2 is as low as about 3.9. In order to realize a transistor having a gate length (Lg) of 0.1 micrometers or less, it is necessary to set the thickness of the gate insulating film to 3 nm or less. However, in the case of a transistor having such a thin silicon oxide film, it is predicted that an increase in the leak current between the gate and a substrate becomes a problem because carriers may tunnel through the film directly. This trade-off relation is an essential problem as long as SiO2 is used as a gate insulating film, and it is thought that its evasion is impossible.
On the other hand, by using a high dielectric material having a relative dielectric constant larger than SiO2, a gate insulating film is formed thickly and it is possible to avoid such a tunneling phenomenon. As the materials, metal oxide, such as ZrO2, HfO2, or compounds of these oxides and SiO2 (so-called “silicate”), etc. can be used.
Since the relative dielectric constant of such high dielectric material is as high as about ten or more, it becomes possible to increase the thickness twice or more compared with SiO2 while obtaining the same gate capacitance. Thus, these high dielectric materials are considered to be the promising material which can suppress the tunneling of carriers.
However, the Inventors have discovered that a problem which is explained below arose, in a case where a semiconductor device which has the gate insulating film using such high dielectric material was manufactured according to the normal manufacturing process.
FIGS. 25A through 26C are process sectional diagrams showing principal parts of manufacturing process of MISFET (MIS Field Effect Transistor) according to a usual process flow.
First, as shown in FIG. 25A, an isolation layer 101 which consists of an insulating material is formed near the surface of the silicon semiconductor layer 100, and the gate insulating film 102 is further formed on the semiconductor layer 100.
Next, as shown in FIG. 25B, a polycrystalline silicon layer 103 used as a gate electrode is formed on the gate insulating film 102. Next, as shown in FIG. 25C, a pattering of the polycrystalline silicon layer is carried out, and the gate electrode 103 is formed. Next, as shown in FIG. 26A, a patterning of the gate insulation film 102 is carried out.
Then, as shown in FIG. 26B, an oxidization process for rounding the corners of the gate electrode 103 is carried out. That is, oxide portions 105 are formed at the corners of the gate electrode 103.
This rounding process is effective especially in order to ease the concentration of the electric field at the corners of the gate electrode 103, and to recover the damages incorporated at the end of the gate insulation film 102 at the time of processing of the gate electrode 103 or an ion implantation for the extensions.
As illustrated in FIG. 26B, on the occasion of this oxidization process, SiO2 films 104 and 105 of the usual thickness are formed on the surfaces of the semiconductor layer 100 and the gate electrode 103.
However, when high dielectric material, such as ZrO2, HfO2 and these silicates, mentioned above, is used as a gate insulating film 102, the thick interface oxidization layers 105 which include SiO2 as the main ingredients are formed in the upper and lower sides of the gate insulating film 102.
When the gate length is long, or when the heat process for oxidization is short, the interface oxidization layer 105 such as the one shown in FIG. 26B is formed. This oxidation layer 105 has a shape of wedge whose thickness becomes thinner near the center of the gate. On the other hand, when the gate length is short, or when the heat process for oxidization is long, as shown in FIG. 26C, the thick uniform interface oxidization layers 105 which penetrate above and below the gate insulating film 102 from both sides are formed.
Such a phenomenon in which the interface oxidization layer 105 is formed in the upper and lower sides of the gate insulating film 102 does not appear when SiO2 or SiON is used as the gate insulating film. This is a characteristic phenomenon which becomes remarkable, when high dielectric material, such as metal oxides, such as ZrO2, HfO2, and these silicates, is used. This phenomenon is considered to originate in a fact that oxygen (O) tends to diffuse in the gate insulating film using such high dielectric materials, compared with the case where SiO2 and SiON are used, and the oxygen becomes active to oxidize the surrounding silicon.
However, since the interface oxidization layer 105 which consists of such a silicon oxide has the small dielectric constant, it has a bad influence on the property of the transistor obtained. Specifically, the following problems arise:
(1) A threshold becomes very high. Especially, when gate length (Lg) becomes short, the threshold becomes very high because the thickness of the interface oxidization layer 105 increases.
(2) Current driving force decreases.
(3) Properties, such as a threshold and driving force, vary from element to element.
Moreover, traps are apt to be generated in the interface of the gate insulating film 102 made of a high dielectric material and the interface oxidization layer 105 formed without being controlled in this way. Especially when the traps are generated at a drain corner, they serve as trap sites of hot carriers. For this reason, another problem that the reliability of a transistor is degraded is also produced.
In recent years, instead of polycrystalline silicon, metal or silicide may be used as a material of the gate electrode 103. In such a case, oxidization which is shown in FIGS. 26B or 26C may not necessarily be performed. However, even in such a case, CVD (Chemical Vapor Deposition) process for formation of a gate side wall is surely required. In this CVD process, the similar interface oxidization layer 105 as what was mentioned above about FIGS. 26B and 26C by the oxygen in atmosphere gas or the remaining oxygen in a vacuum is formed, and there is a possibility that the problem of degrading the operating characteristic and reliability of MISFET may arise.